1. Field of the Invention
The present invention relates to a resampling address generator.
2. Description of the Related Art
The sampling frequency of digital audio data is set to 48 kHz or 32 kHz for digital audio tape (DAT) recording and satellite broadcasting, and is set to 44.1 kHz for compact disks (CDs) (including CDs recordable (CD-Rs) and CDs rewritable (CD-RWs)) and MiniDiscs (MDs). Accordingly, for example, when digital audio data obtained from a DAT or satellite broadcasting is recorded on a CD-R or MD, the sampling frequency must be converted to 44.1 kHz. Conversely, when digital audio data is obtained from a CD or MD, the sampling frequency must be converted to 48 kHz.
FIG. 10 shows the relationship in time domain between input data Di (digital audio data before the conversion of the sampling frequency) and output data Do (digital audio data after the conversion of the sampling frequency). In the following description, the sampling period of the input data Di is represented by Tsi, the sampling period of the output data Do is represented by Tso, the sampling frequency of the input data Di is represented by fsi where fsi=1/Tsi, and the sampling frequency of the output data Do is represented by fso where fso=1/Tso. FIG. 10 also shows a case in which Tsi>Tso. In this case, Tsi=1/44.1 kHz, and Tso=1/48 kHz.
Accordingly, for converting the sampling frequency, as FIG. 11 shows, the input data Di is written with a period Tsi into a ring buffer, and from the input data Di, interpolation data is created at each point of the output data Do. The interpolation data is extracted as the output data Do. 
In this Specification, the difference (shown in FIG. 11) between a read address and a write address in the ring buffer is called a “phase difference”.
FIG. 12 shows an example of sampling frequency conversion, where a sampling frequency of 44.1 kHz is converted to 48 kHz. In part A of FIG. 12, the crosses indicate samples of the input data Di at 1/44.1-kHz intervals, and the circle indicates a typical sample of the output data Do. The point (resampling point) of the output data Do is determined by an output clock signal.
As part B of FIG. 12 shows, the input data Di is oversampled to form data Db having an eight-fold sampling frequency. The triangles indicate interpolation data formed by the oversampling. The oversampling is smoothly performed by using many samples of the input data Di. 
As part C of FIG. 12 shows, the data Db is oversampled to form data Dc having a 64-fold sampling frequency. The squares indicate interpolation data formed by the oversampling. The oversampling is also smoothly performed by using many samples of the input data Db. At this time, the sampling frequency of the data Dc is 512 times (=8×64 times) that of the original input data Di. 
As parts C and D of FIG. 12 show, in the data Dc, from data D1 and data D2 at points t1 and t2 adjacent to a point tn of the output data Do, output data Do is formed by linear interpolation. As is clear from the description of parts C and D of FIG. 12, it is not necessary to form all the samples of the data Dc. Only the data D1 and D2 may be formed as the data Dc. 
In addition, when the data Do is formed by linear interpolation, no problem occurs if the resampling point tn (the point of the data Do) is within the required time precision. For example, the time interval between the data D1 and the data D2 is divided into 4096 lengths, and among the boundary (time) points between the lengths, the data Do may be obtained at the point closest to the resampling point tn. In other words, assuming that the sampling frequency of the input data D, is 44.1 kHz, when the length of one period of the data Dc (D1, D2) having a sampling frequency which is 512 times 44.1 kHz is divided into 4096 lengths, the divided length is approximately 11 picoseconds (1/44.1 kHz×512×4096). Thus, the error at the resampling point tn is 11 picoseconds or less. This precision is sufficient.
As described above, in the conversion in FIG. 12, the data Do and the resampling point can be controlled to have sufficient precision even if the sampling frequency is converted.
The points t1 and t2 are determined by an input-side clock, while the point tn at which the output data Do is obtained is determined by an output-side clock and is not related to the input-side clock. Thus, there is no limitation on the relationship between the input sampling frequency (the sampling frequency of the input data Di) and the output sampling frequency (the sampling frequency of the output data Do). Accordingly, the conversion circuit for the sampling frequency can be formed as an asynchronous type.
FIG. 13 shows an example of a conversion circuit for realizing the above-described sampling frequency conversion. In this conversion circuit, input data Di is supplied to an oversampling filter 11 and it generates data Db having a sampling frequency eight times that of the input data Di. The data Db is sequentially written into a buffer memory 12 while being synchronized with an input-side clock Ci, and is read while being synchronized with an output-side clock Co. In this case, the buffer memory 12 has a ring buffer structure and is used to temporarily store the data Db and to absorb the difference in sampling frequency between the input data Di and the output data Do. 
The data Db read from the buffer memory 12 is supplied to an oversampling filter 13 having a finite impulse response (FIR) filter structure and it generates data Dc (data D1, data D2). The data Dc is supplied to an interpolation circuit 14, and the data D1 and the data D2 are processed by linear interpolation to generate output data Do, which is extracted.
In this case, as shown in, for example, in part D of FIG. 12, the output data Do obtained by linear interpolation is represented byDo=a1/(a1+a2)·D2+a2/(a1+a2)·D1 where a1 represents the time length from the point t1 to the point tn, and a2 represents the time length from the point tn to the point t2. Each of the values a1 and a2 can be obtained by counting the input clock Ci in the length that is, for example, 65536 times the sampling period Tso of the output data Do.
Accordingly, the conversion circuit in FIG. 13 includes an address forming circuit 20. In the address forming circuit 20, based on the input clock Ci, a write-address signal Aw that is synchronized therewith is formed and supplied to the buffer memory 12. A read-address signal Ar synchronized with the output clock Co is formed based on the input clock Ci and the output clock Co by the address forming circuit 20, and is supplied to the buffer memory 12, the oversampling filter 13, and the interpolation circuit 14.
The following two methods 1 and 2 are known as a method for, by the address forming circuit 20, forming the read-address signal Ar, that is, the address of the resampling point. In method 1, the period of the output clock Co is measured in units of each period of the input clock Ci, and the measured value is used to obtain the address of the resampling point. In method 2, by feeding back the difference in period between the input clock Ci and the output clock Co the address of the input clock Ci and the output clock Co can be obtained. Method 2 is called the “phase-locked loop (PLL) method”.
In the case of method 1, assuming that the sampling frequency fsi of the input data Di=44.1 kHz, and the sampling frequency fso of the output data Do=48 kHz,                                           f            si                    ⁢                      :                    ⁢                      f            so                          =                  44.1          ⁢                                           ⁢          kHz          ⁢                      :                    ⁢          48          ⁢                                           ⁢          kHz                                        =                  235.2          ⁢                      :                    ⁢          256                    
Thus, in the measurement of the period Tso by directly using the input clock Ci and the output clock Co, the period Tso of the output clock Co cannot correctly be measured.
Accordingly, actually, as FIG. 14 shows, by counting the input clock Ci during a long time, for example, approximately 1.4 seconds (=Tso×65536), the length of 65536 periods of the output clock Co is measured. From the measured value, the period of the address of the resampling point is found and accumulatively added, whereby the address of the resampling point is formed.
In the case of method 2, as FIG. 15 shows, by integrating the difference in address between the write address and the read address, the period of the address of the resampling point is found and accumulatively added. Also, by feeding back the output of an accumulative adder, the address of the resampling point is formed.
Nevertheless, method 1 has a limitation on an increase in precision when the measuring time is finite. Also, an increased measuring time for increasing the precision causes a discrepancy in that instantaneous precision decreases because the difference between the measured value and the actual time increases.
Method 2 employs feedback control in proportional to the difference between the write address and the read address. Thus, the essential properties of this type of control system are regarded as problems. Specifically, the problems are as follows:
(i) The control holds based on an error;
(ii) The time phase delay of the control system generates transient response characteristics; and
(iii) Remaining jitter or an acoustically unnatural transient change occurs to affect sound quality, even if the transmission system is improved by using a digital filter, etc.